1. Field of the Invention
This invention relates to a successive approximation analog to digital converter that has a large input range and that is capable of continuous conversion cycles without the need to reset the selection and control logic of the converter.
2. Description of the Related Art
Successive approximation analog-to-digital converters (A/D) are well known in the art. A conventional successive approximation analog to digital converter is shown in FIG. 1. In this FIG., an analog voltage V.sub.in 110 is supplied to one input port of a comparator 130. The other input of the comparator 130 receives an output signal from a digital-to-analog converter (D/A) 150. At the start of the most significant bit (MSB) comparison, the digital-to-analog converter 150 receives a digital input value equal to one-half the maximum digital value that it can accept from the successive approximation logic 170 under control of the selection and control logic 190. For example, with an eight-bit D/A, the initial input value to the D/A would then be 10000000 (=bits a.sub.7 a.sub.6 a.sub.5 a.sub.4 a.sub.3 a.sub.2 a.sub.1 a.sub.0).
Therefore, the analog voltage V.sub.in 110 is initially compared to an analog value output from the D/A 150 corresponding to the digital input of 10000000, which is approximately the analog mid-range voltage. If the analog voltage V.sub.in 110 is greater than this analog mid-range voltage, then the MSB of the D/A 150 is set to a "one" for the rest of the A/D conversion process. If the analog voltage V.sub.in 110 is less than this analog mid-range voltage as determined by the output of the comparator 130, then the MSB of the eight-bit digital input to the D/A 150 is set to a "zero" for the rest of the A/D conversion process.
The conversion process then proceeds to the next highest digital bit, which in this instance is the bit a.sub.6. Bit a.sub.6 is set to a "one" during the bit a.sub.6 comparison, and V.sub.in 110 is compared to the D/A output due to a digital input of either 11000000 or 01000000, depending upon whether the MSB has been set to a "one" or a "zero" based on the MSB comparison just completed, as discussed previously. Based on the output of the comparator 130, the next-most MSB of the digital word (i.e., bit a.sub.6) is thereby determined.
This process continues all the way down to the least significant bit a.sub.0, and by this procedure, an eight-bit digital word can be obtained by successive approximation means in as little as eight clock cycles, not counting clock cycles required for addressing and selecting the A/D.
In conventional successive approximation A/Ds as shown in FIG. 1, one needs to reset the selection and control logic 190 for the A/D each time an n-bit conversion cycle commences, since the conventional A/D requires a leading address cycle prior to each read of the A/D. A conventional A/D requires multiple addressing to perform consecutive reads, resulting in an n-bit word needed to address and set up the A/D chip, and another n-bit word needed to retrieve the digital data from the A/D over the output data bus. For an eight bit A/D, this results in 16 clock cycles per each eight-bit read of the A/D.
In addition, the comparator 130 of the conventional A/D limits the allowable range of the input analog voltage V.sub.in 110 to within the allowable input voltage range of the comparator 130. This range may be less than the range desired for conversion purposes.
It is therefore desirable to have a successive approximation A/D that allows continuous conversion cycles without the need to reset the selection and control logic of the A/D, and to thereby allow any number of successive reads after a single address cycle.
It is also desirable to have a successive approximation A/D that allows a greater range of analog input signals to be converted to digital signals by the A/D.